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Gallium nitride (GaN) devices used in power converters offer several advantages including higher efficiency, power density, and high-frequency switching. The lateral GaN high electron mobility transistor (HEMT) power device has seen strong market growth in such applications. The gate drive of this intrinsically depletion-mode device is challenging, with many solutions offered to transform this for a robust enhancement-mode operation. In this article, we summarize a presentation made at the APEC 2024 conference by Bixuan Wang, CPES, Virginia Tech, USA, and a team that included staff from Cambridge GaN Devices, UK. In this work, the gate overvoltage robustness of the p-gate GaN HEMT that features an integrated gate interface and protection is studied.
Some challenges with the p-gate GaN HEMT
Amongst the various options to create an enhancement mode GaN technology, the p-gate GaN HEMT has emerged as a popular device of choice. The addition of a Magnesium doped p-type layer under the gate metal serves to shift the bandgap and hence the threshold voltage Vth of the device into the positive range. The Schottky metal barrier version of this device (SP-HEMT) has been commercialized by many device manufacturers and foundries, with a voltage class range from 15 to 650 V. The Vth of this device is typically below 2V. This low Vth can make the device more susceptible to noise, especially from transients created from the high frequency, high slew rate switching that these devices are capable of.
The parasitic turn-on of the device is a risk from the drain-gate Miller capacitance coupling. This risk often necessitates the use of a negative off-state gate voltage (VGS) drive. Another limitation comes from reliability issues created by the use of a higher voltage gate drive at turn-on. The gate contact typically starts conducting at a VGS > 7 V. Trap-related effects create threshold voltage changes, and hot carriers can also result in dynamic on-state resistance (RDSon) increases. This creates an upper window for on-state VGS, typically around 6.5 V.
The lower window for on-state Vgs can be set by the RDSon, which typically needs > 4V or so to reach a saturated low level. Hence the overall window of operation can be small (4V – 6.5V). The margin for gate overdrive is therefore very limited (around 1 V). Standard gate drivers based on driving Si MOSFETs cannot be used easily, requiring several external components and hence driving up the converter board complexity and cost. Board design and layout can be critical to keeping inductive paths small, and this complexity is increased with a GaN device that has a low noise margin and many external components to interface with the gate driver.
The Integrated GaN Solution
Cambridge GaN Devices is a fabless semiconductor company that has developed a range of GaN-on-silicon power devices rated at 650 V. A novel gate interface, termed the ICeGaN
, as well as sense and protection circuitry are monolithically integrated into a single die solution. A schematic block diagram of the ICeGaN circuit is shown in Figure 1. The main power HEMT is a Schottky p-gate GaN HEMT rated at 650V and a Vth of around 1.6V.
The auxiliary low voltage GaN HEMT, along with the current source and voltage limiter, is responsible for absorbing a large fraction of the externally applied gate voltage. The voltage seen at the gate of the power HEMT device (termed the Inner Gate or VGi in Figure 1) is thus carefully controlled. This circuitry ensures that the power HEMT does not turn on till the external gate voltage VG has reached around 2.7 V (this is the integrated device Vth), at which point VGi sees around 1.6 V. For voltages above this when VG < 7 V, VGi follows gate voltage of the auxiliary HEMT VG,aux per the equation VGi = VG,aux – VGS,aux. At VG > 7V, the VG, aux is clamped at a constant voltage and hence VGi is limited to around 5.5 V.
circuit (Source: Cambridge GaN Devices)The relationship between VG and VGi is illustrated in Figure 2. This therefore allows standard gate drivers to be used for the external VG. Another advantage of the ICeGaN interface is that the clamping circuit creates a reduction in VGi at high VG values at low temperatures relative to elevated temperatures, hence minimizing one of the degradation mechanisms seen in GaN HEMTs1.
The Miller Clamp is an important protection device under dynamic operation. This device has a tunable state such that it is in a high impedance off-state under normal conditions when the power GaN is on. At turn-off, it is capable of strongly pulling VGi to 0 V, accelerating the turn-off and minimizing gate charge. The Miller clamp also provides strong immunity against parasitic turn-on during external transients and fast switching events.
circuit (Source: 1)Gate Over-Voltage Robustness
In this study conducted by Wang and his group, the dynamic gate overvoltage boundaries of the ICeGaN are studied. A 650V/130 mΩ ICeGaN product is used. The smart interface is powered by an external 12 – 20 V VDD voltage, as shown in Figure 1. A resonant voltage overshoot is generated either at VG or VGi, which mimics the gate overshoot that can be seen in power converters. The test is performed under both a static condition where the power GaN drain-source is grounded (termed DSG, with VDS = 0V) which mimics the zero-voltage switching case, as well as a hard switching (HSW) condition at a 400 V bus-voltage and an inductive load. The test platform schematics are shown in Figure 3.
This test circuit generates an overshoot by building up energy in the gate loop inductor LG, which is charged by the 0.5 V VCC supply voltage. Switch S1 is a low-voltage GaN HEMT. When S1 is turned off the energy in LG creates a resonant overshoot, with the resonance created by LG and the sum of the input capacitance of the ICeGaN and the output capacitance of S1. The pulse width of the overshoot can be modulated by the LG value and the overshoot by the on time of S1. A 20 ns width was used in this work. The devices were tested at 25oC and 150oC. Another variable used was the VDD supply of the ICeGaN chip. In one case this was set to 20 V, while in another case it was tied to the external gate supply. The latter condition removes overvoltage stress in the ESD protection circuit.
The dynamic gate overvoltage robustness is measured by the parameter BVG, DYN which indicates the maximum gate overstress voltage before the part fails. The results obtained are shown in the Table included in Figure 3. With the overvoltage applied directly to the internal gate, a BVG, DYN value of 33-35 V is obtained, while this is increased to 66 -72 V when the stress is applied to the external gate pin of the ICeGaN with the VDD at 20 V. When the VDD pin is shorted to the external gate, the BVG, DYN further increase to 84 -92 V. Failure analysis in the case where the VDD is driven by an external 20 V supply indicates that the ESD protection block in the ICeGaN chip was the likely failure block. The parametric characteristics at fail show a gate-source short. The failure in the case where the VDD was shorted to the external gate showed minimal shifts in the transfer characteristics after failure. The failure here is attributed to the degradation in the Miller clamp, leading to a soft failure.
The significant boost demonstrated in BVG, DYN shows the excellent gate protection provided by the ICeGaN gate interface. This improvement in gate robustness through an integrated solution can be an essential benefit in the use of the ICeGaN device in power converter applications.
References
1 K. Mukherjee, M. Arnold, J. Zhang, K. Ledins, M. Michalak, O. Fung, L. Efthymiou, Z. Ansari, G. Longobardi, F. Udrea, “Characterization of the novel ICeGaN 650V/ 8.5 A, 200 mΩ power device technology”, published on ScienceDirect
The post Gate Overvoltage Robustness in Integrated Circuit p-Gate GaN HEMT appeared first on Power Electronics News.
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